EDA 急等啊
追答去年学的,不知道和你们是不是一样,我是按模块编写的
主程序:
module clock(clk,clk1,clr,a,b,c,d,e,f,g,sel);
input clk,clk1,clr;
output a,b,c,d,e,f,g;
output [2:0]sel;
wire [7:0]qm,qf,qs;//秒,分,时
wire c0,c1;
wire [2:0]sel;
wire k0,k1;
wire [3:0]num;
c60 c60A(.clk(clk1),.clr(clr),.q(qm),.c(c0));//秒钟计时
c60 c60B(.clk(c0), .clr(clr),.q(qf),.c(c1));//分钟计时
c24 c24A(.clk(c1), .clr(clr),.q(qs));//小时计时
mux81 mux81A(.A(qm[3:0]),.B(qm[7:4]),.C(4'b1010),.D(qf[3:0]),.E(qf[7:4]),.F(4'b1010),.G(qs[3:0]),.H(qs[7:4]),.S(sel),.Q(num));
c_scan8 scanA(.clk(k0),.clr(clr),.q(sel));//扫描数码管
div_clk clkA(.clk(clk),.clr(clr),.ck0(k0),.ck1(k1));//分频
clk_deled clk_deledA(.num(num),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));//数码管段选
endmodule
各模块如下:
module C60(clk,clr,q,c);
input clk,clr;
output [7:0]q;
output c;
reg [7:0]q;
reg c;
always @(posedge clk or negedge clr)
begin if(!clr) begin q=8'H0;c=1'H0; end
else begin if(q[3:0]<4'H9 ) q[3:0]=q[3:0]+4'H1;
else begin q[3:0]=0;
if(q[7:4]<4'H5)
begin q[7:4]=q[7:4]+4'H1;
c=1'H0;
end
else begin q[7:4]=4'H0;c=1'H1; end
end
end
end
endmodule
module C24(clk,clr,q);
input clr,clk;
output [7:0]q;
reg [7:0]q;
always @(posedge clk or negedge clr)
begin if(!clr) q[7:0]=0;
else begin if(q[7:0]<8'H23)
begin if(q[3:0]<4'H9) q[3:0]=q[3:0]+4'H1;
else begin q[3:0]=0;
q[7:4]=q[7:4]+4'H1;
end
end
else q[7:0]=0;
end
end
endmodule