怎么用加法计数器实现两个100以内十进制数相加,结果用七段显示译码器显示

Question

关于数电的设计

Answer 1

我会点译码显示部分 参考下：module LED_Display(clk_n,seg,dp,an);
input clk_n;
output [6:0]seg;
output dp;
output [7:0] an;
reg [15:0] count_for_clk;
reg [7:0] an_reg=0;
reg [6:0] seg_reg=0;

assign seg=seg_reg;
assign dp=1;
assign an=an_reg;

parameter
zero =7'b100_0000,
one =7'b111_1001,
two =7'b010_0100,
three=7'b011_0000,
four =7'b001_1001,
five =7'b001_0010,
six =7'b000_0010,
seven=7'b111_1000,
eight=7'b100_0000,
nine =7'b001_0000;

//分频计数器

always@(posedge clk_n) begin
count_for_clk<=count_for_clk+1;
end
//段选寄存器赋值，8位数码管分时复用
always@(posedge clk_n) begin
case(count_for_clk[15:13])
0: seg_reg<=one;
1: seg_reg<=two;
2: seg_reg<=three;
3: seg_reg<=four;
4: seg_reg<=five;
5: seg_reg<=six;
6: seg_reg<=seven;
7: seg_reg<=eight;
endcase
end
//位选寄存器赋值，每次只选通一位数码管
always@(posedge clk_n) begin
case(count_for_clk[15:13])
0: an_reg<=8'b1111_1110;
1: an_reg<=8'b1111_1101;
2: an_reg<=8'b1111_1011;
3: an_reg<=8'b1111_0111;
4: an_reg<=8'b1110_1111;
5: an_reg<=8'b1101_1111;
6: an_reg<=8'b1011_1111;
7: an_reg<=8'b0111_1111;
endcase
end
endmodule