library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vote5 is
port(v_in:in std_logic_vector(4 downto 0);
lock,clr:in std_logic;
v_over:out std_logic_vector(2 downto 0);
num_agr,num_opp:out std_logic_vector(3 downto 0);
v_out:out std_logic_vector(4 downto 0);
led_agr,led_opp:out std_logic);
end entity vote5;
architecture one of vote5 is
begin
process(clr,v_in,lock)
variable agr,opp: std_logic_vector(3 downto 0);
begin
if(clr='1')then
led_agr<='0';
led_opp<='0';
agr:="0000";
opp:="0000";
if agr="0000" then
num_agr<="0000";
end if;
if opp="0000"then
num_opp<="0000";
end if;
v_out<="00000";
v_over<="000";
elsif(lock'event and lock='1')then
v_out<=v_in;
v_over<="111";
agr:="0000";
opp:="0000";
for i in 0 to 4 loop
if (v_in(i)<='0') then opp:=opp+1;
end if;
if(v_in(i)<='1')then agr:=agr+1;
end if;
end loop;
num_agr<=agr;
num_opp<=opp;
if(agr>opp)then
led_agr<='1';
led_opp<='0';
else
led_agr<='0';
led_opp<='1';
end if;
end if;
end process;
end architecture one;