第1个回答 推荐于2017-09-17
use ieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock_shu is
port(
clk : in std_logic;
reset : in std_logic;
duan : out std_logic_vector(5 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end;
architecture a of clock_shu is
component count60
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end component;
component count24
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end component;
component i60bcd
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;
component i24bcd
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;
signal carry1,carry2 : std_logic;
signal abin1,abin2 : integer range 0 to 59;
signal abin3 : integer range 0 to 23;
signal clk_1h : std_logic;
signal sh,sl,mh,ml,hh,hl : std_logic_vector(7 downto 0);
signal cnt : integer range 0 to 5 :=0;
begin
process(clk)--分频为1hz
constant counter_len:integer:=19999999;
variable cnt:integer range 0 to counter_len;
begin
if clk'event and clk='1' then
if cnt=counter_len then
cnt:=0;
else
cnt:=cnt+1;
end if;
case cnt is
when 0 to counter_len/2=>clk_1h<='0';
when others =>clk_1h<='1';
end case;
end if;
end process;
process(clk)
variable cnt1 : integer range 0 to 200;
variable cnt2 : integer range 0 to 10;
begin
if clk'event and clk='1' then
if cnt1=200 then
cnt1:=0;
if cnt2=10 then
cnt2:=0;
if(cnt=5)then
cnt<=0;
else
cnt<=cnt+1;
end if;
else
cnt2:=cnt2+1;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end process;
process(clk)
begin
if clk='1' then
case cnt is
when 0 => duan<="000001";data_o<=sl;
when 1 => duan<="000010";data_o<=sh;
when 2 => duan<="000100";data_o<=ml;
when 3 => duan<="001000";data_o<=mh;
when 4 => duan<="010000";data_o<=hl;
when 5 => duan<="100000";data_o<=hh;
when others=>duan<="000000";
end case;
end if;
end process;
u1 : count60 port map(carry=>clk_1h,rst=>reset,times=>abin1,full=>carry1);
u2 : count60 port map(carry=>carry1,rst=>reset,times=>abin2,full=>carry2);
u3 : count24 port map(carry=>carry2,rst=>reset,times=>abin3);
u4 : i60bcd port map(interg=>abin1,ten=>sh,one=>sl);
u5 : i60bcd port map(interg=>abin2,ten=>mh,one=>ml);
u6 : i24bcd port map(interg=>abin3,ten=>hh,one=>hl);
end;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count60 is--分，秒计数器
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end;
architecture a of count60 is
signal time_s : integer range 0 to 59;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
full<='0';
elsif rising_edge(carry) then
if time_s=59 then
time_s<=0;
full<='1';
else
time_s<=time_s+1;
full<='0';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count24 is--时计数器
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end;
architecture a of count24 is
signal time_s : integer range 0 to 23;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
--full<='0';
elsif rising_edge(carry) then
if time_s=23 then
time_s<=0;
--full<='1';
else
time_s<=time_s+1;
--full<='1';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i60bcd is--分，秒显示
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;
architecture a of i60bcd is
begin
process(interg)
begin
case interg is
when 0|10|20|30|40|50 => one<="11000000";
when 1|11|21|31|41|51 => one<="11111001";
when 2|12|22|32|42|52 => one<="10100100";
when 3|13|23|33|43|53 => one<="10110000";
when 4|14|24|34|44|54 => one<="10011001";
when 5|15|25|35|45|55 => one<="10010010";
when 6|16|26|36|46|56 => one<="10000011";
when 7|17|27|37|47|57 => one<="11111000";
when 8|18|28|38|48|58 => one<="10000000";
when 9|19|29|39|49|59 => one<="10011000";
when others => one<=null;
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23|24|25|26|27|28|29 => ten<="10100100";
when 30|31|32|33|34|35|36|37|38|39 => ten<="10110000";
when 40|41|42|43|44|45|46|47|48|49 => ten<="10011001";
when 50|51|52|53|54|55|56|57|58|59 => ten<="10010010";
when others => ten<=null;
end case;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity i24bcd is--时显示
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;
architecture a of i24bcd is
begin
process(interg)
begin
case interg is
when 0|10|20 => one<="11000000";
when 1|11|21 => one<="11111001";
when 2|12|22 => one<="10100100";
when 3|13|23 => one<="10110000";
when 4|14 => one<="10011001";
when 5|15 => one<="10010010";
when 6|16 => one<="10000011";
when 7|17 => one<="11111000";
when 8|18 => one<="10000000";
when 9|19 => one<="10011000";
when others => one<=null;
end case;
case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23 => ten<="10100100";
when others => ten<=null;
end case;
end process;
end;本回答被提问者采纳