用Verilog设计一位十进制可逆计数器？

Question

如题所述

Answer 1

module test (
input cp,
input asclr,
input preset,
input [3:0] psdata,
input up,
output reg [3:0] cntvalue,
output reg cout
);
 
 
always @(posedge cp or negedge asclr)
if ( !asclr) begin
cntvalue <= 4'h0;  
cout <= 1'b0; 
end
else if (preset==1) begin
cntvalue <= psdata;
cout <= 1'b0; 
end
else if ( up ==1) begin
if ( cntvalue < 4'h9) begin
cntvalue <= cntvalue +1;
end
else begin
cntvalue <= 4'h0; 
cout <= 1'b1;
end
end
else if ( !up) begin
if (cntvalue == 4'h0) begin
cntvalue <= 4'h9;
cout <= 1'b1;  
end
else begin
cntvalue <= cntvalue -1;
end
end
 
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