用VHDL语言设计8位加1计数器,该计数器含有异步清零端，计数使能端和进位输出端。

Question

如题所述

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count8 is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
cm : out std_logic;
c_out : out std_logic_vector(7 downto 0)
);
end count8;

architecture arc of count8 is

signal cnt : std_logic_vector(7 downto 0);

begin

process(clk,rst)
begin
if rst = '1' then
cnt <= (others=>'0');
cm <= '0';
elsif rising_edge(clk) then
if en = '1' then
if cnt = "11111111" then
cm <= '1';
cnt <= "00000000";
else
cnt <= cnt + 1;
cm <= '0';
end if;
end if;
end if;
end process;

c_out <= cnt;

end arc;

是这么个意思么？本回答被提问者采纳