题目：设计一个具有异步清零的32位二进制的减法计数器！，请将具体的VHDL代码发给我一下 谢谢！

Question

如题所述

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY DCLK IS
PORT(CLK:IN STD_LOGIC;
READY:IN STD_LOGIC;
STA:IN STD_LOGIC;
start:IN STD_LOGIC_VECTOR(7 DOWNTO 0);--一般单片机只需输出8为
CONTROL:IN STD_LOGIC_VECTOR(1 DOWNTO 0);--选择初值，将32位分成4个8位
SO1:OUT STD_LOGIC;
SO2:OUT STD_LOGIC;
SO3:OUT STD_LOGIC;
out1:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
out2:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
out3:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
out4:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY DCLK;
ARCHITECTURE ART OF DCLK IS
SIGNAL SUB1:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SUB2:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SUB3:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SUB4:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS (READY,CLK,STA) IS
variable S1:STD_LOGIC;
variable S2:STD_LOGIC;
variable S3:STD_LOGIC;
BEGIN
IF READY='1' THEN--清零信号
SUB1<="00000000";
SUB2<="00000000";
SUB3<="00000000";
SUB4<="00000000";
ELSIF STA='1' THEN--赋初值信号
CASE CONTROL IS
WHEN"00"=>SUB1<=START;
WHEN"01"=>SUB2<=START;
WHEN"10"=>SUB3<=START;
WHEN"11"=>SUB4<=START;
END CASE;

elsIF (CLK'EVENT AND CLK='1' )THEN --实现32位减法
IF SUB1="00000000" THEN
SUB1<="11111111";
S1:='0';
ELSE
SUB1<=SUB1-1;
S1:='1';
END IF;
IF (SUB2="00000000"AND S1='0') THEN
SUB2<="11111111";
S1:='1';
S2:='0';
ELSif S1='0' THEN
S1:='1';
S2:='1';
SUB2<=SUB2-1;
END IF;
IF (SUB3="00000000"AND S2='0') THEN
SUB3<="11111111";
S2:='1';
S3:='0';
ELSIF (S2='0') THEN
S2:='1';
S3:='1';
SUB3<=SUB3-1;
end if;
IF (SUB4="00000000"AND S3='0') THEN
SUB4<="11111111";
S3:='1';
ELSIF ( S3='0') THEN
S3:='1';
SUB4<=SUB4-1;

END IF;
END IF;
OUT1<=SUB1;
OUT2<=SUB2;
OUT3<=SUB3;
OUT4<=SUB4;
END PROCESS;
END ART;

仿真过了，是ok的