求：十进制减法计数器的Verilog HDL仿真测试程序
模块描述有了、但是要仿真、缺少测试模块、希望哪位大虾帮忙写下是以`timescale 1ns/1ns 这种形式开头的测试模块代码下面的是源程序module CNT10 (CLK, RST, EN, CQ, COUT); input CLK,RST,EN; output[3:0] CQ; output COUT; reg[3:0] CQ,CQI; reg COUT; always @(posedge CLK)//检测时钟上升沿 begin : u1 if (RST == 1'b1)//计数器复位 begin CQI={4{1'b0}}; end begin if(EN==1'b1)//检测是否允许计数 begin if (CQI<9) begin CQI=CQI+1; //允许计数 end else begin CQI={4{1'b0}}; //大于9，计数值清零 end end end if (CQI==9) begin COUT<=1'b1 ; //计数大于9，输出进位信号 end else begin COUT<=1'b0 ; end CQ<=CQI ; //将计数值向端口输出 end endmodule
用的是VHDL
该程序实现的功能：设计一个至少4位的十进制计数器，具有加减计数功能和置数功能，并能通过数码管显示计数结果。减数为零时发声报警。加数为9999时报警
----------这个程序中clk接1KHZ时个位每秒变化一下-------------
-----------D:\VHDL\test\test\four\three\4位数码管级联\加计数----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------
entity countup is
port(clk:in std_logic;
clr:in std_logic;
lad:in std_logic;
en: in std_logic_vector(1 downto 0);
clkup:in std_logic;
sel:out std_logic_vector(1 downto 0);
din:in std_logic_vector(3 downto 0);
pout:buffer std_logic_vector(7 downto 0);
speaker:out std_logic);
end entity countup;
-----------------------------------------------
architecture art of countup is
SIGNAL dout:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL dout0,dout1,dout2,dout3:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL counter:std_logic_vector(1 downto 0);
begin
-----------------进程1---------------------------------------------------
one: --这个进程是数码管从0变到9之后，数码管的位置在依次变化
process(clkup)is
begin
if(en="00")then
if(clkup'event and clkup='1' )then
if clr='1' then dout0<="0000";dout1<="0000";dout2<="0000";dout3<="0000";
elsif lad='1' then dout0<=din;dout1<=din;dout2<=din;dout3<=din;
elsif(dout0>="1001")then dout0<="0000"; ---------显示个位数字
if(dout1>="1001")then dout1<="0000"; ---------显示十位数字
if(dout2>="1001")then dout2<="0000"; --------显示百位数字
if(dout3>="1001")then dout3<="0000";----显示千位数字
else dout3<=dout3+1;
end if;
else dout2<=dout2+1;
end if;
else dout1<=dout1+1;
end if;
else dout0<=dout0+1;
end if;
end if;
end if;
end process;
---------------------------------
process(clk) is
begin
if (clk'event and clk='1') then
if(dout0="1001" and dout1="1001" and dout2="1001" and dout3="1001")then
speaker<='1'; else speaker<='0';
end if;
end if;
end process ;
------------------进程2---------------------------------------
two:
process(clk) is
begin
if (clk'event and clk='1') then
------------------------------------------------
counter<=counter+'1'; ---
case counter is ---
when "00"=>dout<= dout1; ---
when "01"=>dout<= dout2; ---
when "10"=>dout<= dout3; ---
when "11"=>dout<= dout0; ---
when others=>NULL; ---
end case; ---
end if;
---------------------------------
end process two;
sel<=counter;
-----------------进程3--------------------------------------------------
three: --这个进程是进入一个时钟dout就加1，而在数码管上显示的数字就相应的加1；直到数码管从1变化到9
process(dout)is
begin
case dout is
when "0000" => pout<="11111100";
when "0001" => pout<="01100000";
when "0010" => pout<="11011010";
when "0011" => pout<="11110010";
when "0100" => pout<="01100110";
when "0101" => pout<="10110110";
when "0110" => pout<="10111110";
when "0111" => pout<="11100100";
when "1000" => pout<="11111110";
when "1001" => pout<="11110110";
when others => pout<="00000001";
end case;
end process three;
-------------------------------------------------------------------
end architecture art;
----------- D:\VHDL\test\test\four\three\4位数码管级联\减计数--------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------
entity countdn is
port(clk:in std_logic;
clr:in std_logic;
lad:in std_logic;
en: in std_logic_vector(1 downto 0);
clkdn:in std_logic;
sel:out std_logic_vector(1 downto 0);
din:in std_logic_vector(3 downto 0);
pout:buffer std_logic_vector(7 downto 0);
speaker:out std_logic);
end entity countdn;
-----------------------------------------------
architecture art of countdn is
SIGNAL dout,pdout:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL dout5,dout6,dout7,dout8:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL counter:std_logic_vector(1 downto 0);
begin
-----------------进程1---------------------------------------------------
one1: --这个进程是数码管从0变到9之后，数码管的位置在依次变化
process(clkdn)is
begin
if en="01"then
if(dout6="0000" and dout7="0000" and dout8="0000" and dout5="0000")then
speaker<='1';else speaker<='0';
end if;
if(clkdn'event and clkdn='1' )then
if clr='1' then dout5<="0000";dout6<="0000";dout7<="0000";dout8<="0000";
elsif lad='1' then dout5<=din;dout6<=din;dout7<=din;dout8<=din;
elsif(dout5="0000")then dout5<="1001"; ---------显示个位数字
if(dout6="0000")then dout6<="1001"; ---------显示十位数字
if(dout7="0000")then dout7<="1001"; ---------显示百位数字
if(dout8="0000")then dout8<="1001"; ---------显示千位数字
else dout8<=dout8-1;
end if;
else dout7<=dout7-1;
end if;
else dout6<=dout6-1;
end if;
else dout5<=dout5-1;
end if;
end if;
end if;
end process one1;
--------------进程2-------------------------------------------
two:
process(clk) is
begin
if (clk'event and clk='1') then
------------------------------------------------
counter<=counter+'1'; ---
case counter is ---
when "00"=>dout<= dout6; ---
when "01"=>dout<= dout7; ---
when "10"=>dout<= dout8; ---
when "11"=>dout<= dout5; ---
when others=>NULL; ---
end case; ---
end if;
---------------------------------
end process two;
sel<=counter;
-----------------进程3--------------------------------------------------
three: --这个进程是进入一个时钟dout就加1，而在数码管上显示的数字就相应的加1；直到数码管从1变化到9
process(dout)is
begin
case dout is
when "0000" => pout<="11111100";
when "0001" => pout<="01100000";
when "0010" => pout<="11011010";
when "0011" => pout<="11110010";
when "0100" => pout<="01100110";
when "0101" => pout<="10110110";
when "0110" => pout<="10111110";
when "0111" => pout<="11100100";
when "1000" => pout<="11111110";
when "1001" => pout<="11110110";
when others => pout<="00000001";
end case;
end process three;
-------------------------------------------------------------------
end architecture art;
------------pout2选1程序-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------
entity pout is
port(a:in std_logic_vector(7 downto 0);
b:in std_logic_vector(7 downto 0);
c:out std_logic_vector(7 downto 0);
en:in std_logic_vector(1 downto 0));
end entity pout;
-----------------------------------------------
architecture art of pout is
begin
process(en,a,b)is
begin
if en="00"then c<=a;
else c<=b;
end if;
end process one1;
end architecture art;
------------sel2选1程序-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------
entity sel is
port(a:in std_logic_vector(1 downto 0);
b:in std_logic_vector(1 downto 0);
c:out std_logic_vector(1 downto 0);
en:in std_logic_vector(1 downto 0));
end entity sel;
-----------------------------------------------
architecture art of sel is
begin
process(en,a,b)is
begin
if en="00"then c<=a;
else c<=b;
end if;
end process one1;
end architecture art;
module CNT10 (CLK,
RST,
EN,
CQ,
COUT);
input CLK,RST,EN;
output[3:0] CQ;
output COUT;
reg[3:0] CQ,CQI;
reg COUT;
always @(posedge CLK)//检测时钟上升沿
begin : u1
if (RST == 1'b1)//计数器复位
begin
CQI={4{1'b0}};
end
begin
//下面的代码是组合逻辑还是时序逻辑？属于哪个always块？
if(EN==1'b1)//检测是否允许计数
begin
if (CQI<9)
begin
CQI=CQI+1; //允许计数 //如果是时序逻辑，为什么不用非阻塞赋值？如果是组合逻辑，就形成了组合循环，严重错误!
end
else
begin
CQI={4{1'b0}}; //大于9，计数值清零
end
end
end
//下面的代码与上面一样的错误!!!
if (CQI==9)
begin
COUT<=1'b1 ; //计数大于9，输出进位信号
end
else
begin
COUT<=1'b0 ;
end
CQ<=CQI ; //将计数值向端口输出
end
endmodule
总地来说，这是一段无法仿真的代码，错误太多，完全不符合verilog语法规则。