实验目的：
设计一个4位十进制频率计，学习复杂数字系统的设计方法。
实验原理：
根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1秒的脉冲计数允许信号，1秒计数结束后，计数值（即所测信号频率）锁入锁存器，并为下一次测频作准备，即将计数器清零。
试验内容：
1、根据频率计的工作原理，将电路划分成控制器、计数器、锁存器和LED显示几个模块，
控制器——产生1秒脉宽的计数允许信号、锁存信号和计数器清零信号
计数器——对输入信号的脉冲数进行累计
锁存器——锁存测得的频率值
LED显示——将频率值显示在数码管上
顶层文件框图如下：
2、用元件例化语句写出频率计的顶层文件。
提示：十进制计数器输出的应是4位十进制数的BCD码，因此输出一共是4×4bit。
实验结果：
各模块电路的VHDL描述：
10进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (rst,fx,ena:in std_logic;
cout: out std_logic;
outy :out std_logic_vector(3 downto 0));
end cnt10;
architecture behv of cnt10 is
begin
process (rst,ena,fx)
variable cqi :std_logic_vector(3 downto 0);
begin
if rst='1' then cqi :=(others =>'0');
elsif fx'event and fx='1' then
if ena ='1' then
if cqi < 9 then cqi:=cqi+1;cout<='0';
elsif cqi=9 then
cqi :=(others =>'0');
cout<='1';
end if;
elsif ena='0' then cqi:=(others =>'0');
end if;
end if;
outy <=cqi;
end process;
end behv;
4位10进计数器
library ieee;
use ieee.std_logic_1164.all;
entity cnt10_4 is
port(fx,rst,ena:in std_logic;
d:out std_logic_vector(15 downto 0));
end entity;
architecture one of cnt10_4 is
component cnt10
port (rst,fx,ena:in std_logic;
cout: out std_logic;
outy :out std_logic_vector(3 downto 0));
end component;
signal e:std_logic_vector(3 downto 0);
begin
u1:cnt10 port map(fx=>fx,rst=>rst,ena=>ena,cout=>e(0),outy=>d(3 downto 0));
u2:cnt10 port map(fx=>e(0),rst=>rst,ena=>ena,cout=>e(1),outy=>d(7 downto 4));
u3:cnt10 port map(fx=>e(1),rst=>rst,ena=>ena,cout=>e(2),outy=>d(11 downto 8));
u4:cnt10 port map(fx=>e(2),rst=>rst,ena=>ena,cout=>e(3),outy=>d(15 downto 12));
end architecture one;
16位锁存器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity latch4 is
port(d:in std_logic_vector(15 downto 0);
ena,clk:in std_logic;
q:out std_logic_vector(15 downto 0));
end latch4;
architecture one of latch4 is
begin
process(clk,ena,d)
variable cqi:std_logic_vector(15 downto 0);
begin
if ena='0' then cqi:=cqi;
elsif clk'event and clk='1' then cqi:=d;
end if;
q<=cqi;
end process;
end one;
LED控制模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led_controller is
port(d:in std_logic_vector(3 downto 0);
a:out std_logic_vector(6 downto 0));
end led_controller;
architecture one of led_controller is
begin
process(d)
begin
case d is
when "0000"=> a<="0111111";when "0001"=> a<="0000110";
when "0010"=> a<="1011011";when "0011"=> a<="1001111";
when "0100"=> a<="1100110";when "0101"=> a<="1101101";
when "0110"=> a<="1111101";when "0111"=> a<="0000111";
when "1000"=> a<="1111111";when "1001"=> a<="1101111";
when "1010"=> a<="1110111";when "1011"=> a<="1111100";
when "1100"=> a<="0111001";when "1101"=> a<="1011110";
when "1110"=> a<="1111001";when "1111"=> a<="1110001";
when others=> null;
end case;
end process;
end;
控制模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port (clk:in std_logic;
rst,ena: out std_logic);
end control;
architecture behv of control is
begin
process (clk)
variable cqi :std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then
if cqi <1 then cqi:=cqi+1;ena<='1';rst<='0';
elsif cqi=1 then
cqi :=(others =>'0');
ena<='0';rst<='1';
end if;
end if;
end process;
end behv;
总体例化语句：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntf is
port(rset,clk:in std_logic;
fx:in std_logic;
ledout:out std_logic_vector(27 downto 0));
end entity;
architecture one of cntf is
component control
port (clk:in std_logic;
rst,ena: out std_logic);
end component;
component cnt10_4
port(fx,rst,ena:in std_logic;
d:out std_logic_vector(15 downto 0));
end component;
component latch4
port(d:in std_logic_vector(15 downto 0);
ena,clk:in std_logic;
q:out std_logic_vector(15 downto 0));
end component;
component led_controller
port(d:in std_logic_vector(3 downto 0);
a:out std_logic_vector(6 downto 0));
end component;
signal x,z:std_logic;
signal g,h:std_logic_vector(15 downto 0);
signal leds:std_logic_vector(27 downto 0);
begin
u1: control port map(clk=>clk,ena=>x,rst=>z);
u2: cnt10_4 port map(fx=>fx,rst=>z,ena=>x,d=>g);
u3: latch4 port map(clk=>clk,ena=>x,d=>g,q=>h);
u4: led_controller port map(d(3 downto 0)=>h(3 downto 0),a(6 downto 0)=>leds(6 downto 0));
u5: led_controller port map(d(3 downto 0)=>h(7 downto 4),a(6 downto 0)=>leds(13 downto 7));
u6: led_controller port map(d(3 downto 0)=>h(11 downto 8),a(6 downto 0)=>leds(20 downto 14));
u7: led_controller port map(d(3 downto 0)=>h(15 downto 12),a(6 downto 0)=>leds(27 downto 21));
ledout<=leds;
end;
追问有八位十进制的频率计程序么?
追答现成的是没有了，如果你不介意的话可以把这个当做模板做出来。