求EDA课程设计异步复位加减可逆60进制计数器的设计程序

Question

如题所述

Answer 1

VHDL描述：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_60 is
port(clk,reset,m:in std_logic;
c_q:out std_logic_vector(5 downto 0);
c_carry:out std_logic);
end count_60;
architecture behaviour of count_60 is
begin
process(clk,reset)
variable cnt:std_logic_vector(5 downto 0);
begin
if reset='1' then
cnt:="111011";
elsif clk'event and clk='1' then
if m='0' then
if cnt>0 then cnt:=cnt-1;
else cnt:="111011";
end if;
else
if cnt<59 then cnt:=cnt+1;
else cnt:="000000";
end if;
end if;
end if;
if cnt=0 then
c_carry<='1';
else
c_carry<='0';
end if;
c_q<=cnt;
end process;
end behaviour;本回答被网友采纳