引用的东西要在同一个project里的其他文件里有定义才行。
给你个例子看下就明白了,这是引用一位全加器构成一个四位全加器。
project名是adder,里面两个vhd文件,分别为fulladder.vhd和adder.vhd
fulladder.vhd内容如下:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FullAdder is --这是一位全加器
port(
A:in std_logic;
B:in std_logic;
C:in std_logic;
Carry:out std_logic;
Sum:out std_logic
);
END FullAdder;
architecture a of FullAdder is
begin
Sum<=A xor B xor C;
Carry<=(A and B) or (A and C) or (B and C);
end a;
adder.vhd内容如下:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is --四位全加器
port(
A,B:in std_logic_vector(3 downto 0);
S:out std_logic_vector(3 downto 0);
C:inout std_logic_vector(4 downto 0)
);
end adder;
architecture a of adder is
component FullAdder --声明component
port(
A:in std_logic;
B:in std_logic;
C:in std_logic;
Carry:out std_logic;
Sum:out std_logic
);
end component;
begin
u1:FullAdder port map(A(0),B(0),C(0),C(1),S(0));
--引用component,u1,u2,u3,u4为映像的标识名,port map是关键字,端口按对应顺序写
u2:FullAdder port map(A(1),B(1),C(1),C(2),S(1));
u3:FullAdder port map(A(2),B(2),C(2),C(3),S(2));
u4:FullAdder port map(A(3),B(3),C(3),C(4),S(3));
C(0)<='0';
end a;
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