第1个回答 2010-05-05
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div_ry is
port(
clk_in :in std_logic;---------input clk
d:in std_logic_vector(7 downto 0);----------分频系数,根据你实际频率算下,用拨码开关实现
clk_out :out std_logic);-------输出clk
end div_ry;
architecture behav of div_ry is
signal clk_reg :std_logic;
signal cnt :integer;
begin
process(clk_in)
begin
if clk_in'event and clk_in='1' then
if cnt = d then
cnt<=0;
clk_reg<=not clk_reg;
else
cnt<=cnt+1;
end if;
end if;
clk_out<=clk_reg;
end process;
end behav;
能实现