跪求高手翻译一些电气类术语

Question

1.十进制同步加/减计数器（双时钟）
2.简要说明：
193 为可预置的十进制同步加/减计数器，共有
54193/74193，54LS193/74LS193两种线路结构形式。其主
要电特性的典型值如下：
3.193的清除端是异步的。当清除端（CLEAR）为高电平
时，不管时钟端（C DOWN、C UP）状态如何，即可完成
清除功能。
193 的预置是异步的。当置入控制端（LOAD）为低电
平时，不管时钟（C DOWN、C UP）的状态如何，输出端
（QA－QD）即可预置成与数据输入端（A－D）相一致的
状态。
193 的计数是同步的，靠C DOWN、C UP同时加在 4
个触发器上而实现。在C DOWN、C UP上升沿作用下QA－
QD同时变化，从而消除了异步计数器中出现的计数尖峰。
当进行加计数或减计数时可分别利用C DOWN或C UP，此
时另一个时钟应为高电平。
当计数上溢出时，进位输出端（CARRY）输出一个低
电平脉冲，其宽度为 C UP 低电平部分的低电平脉冲；当
计数下溢出时，错位输出端（BORROW）输出一个低电平
脉冲，其宽度为C DOWN低电平部分的低电平脉冲。
当把 BORROW 和 CARRY 分别连接后一级的 C
DOWN、C UP，即可进行级联。
4. 错位输出端（低电平有效）
5. 进位输出端
6. 减计数时钟输入端（上升沿有效）
7.加计数时钟输入端
8.异步清除端
9.并行数据输入端
10.异步并行置入控制端

Answer 1

1. Decimal synchronous up / down counter (Dual Clock)

2. Brief Description:

193 decimal to be synchronized preset up / down counter, a total of

54193/74193, 54LS193/74LS193 two line structure. Its main

To the electrical characteristics of typical values are as follows:

3.193's clear the end is asynchronous. When the clear side (CLEAR) is high

, Whether the clock terminal (C DOWN, C UP) state how to complete

Clearance.

193 preset is asynchronous. When placed in control side (LOAD) for low power

Normally, regardless of the clock (C DOWN, C UP) state how output

(QA-QD) can be preset into the data input (A-D) consistent

State.

193 count is synchronized by C DOWN, C UP also added to the 4

Achieved on a trigger. In the C DOWN, C UP QA-under rising

QD also change, thus eliminating the asynchronous counter counting spikes appear.

When the conduct count plus or minus count, respectively, or using C DOWN C UP, this

Another is high when the clock should.

When the count on the overflow, the carry output (CARRY) outputs a low

Level pulse width for the C UP LOW part of the low pulse; when

Count under the overflow, the displacement output (BORROW) outputs a low

Pulse width for the C DOWN LOW part of the low pulse.

When the BORROW and CARRY are connected to one of C

DOWN, C UP, can be cascaded.

4. Dislocation output (active low)

5. Carry output

6. By counting clock input (rising edge valid)

7. Plus count clock input

8. Asynchronous clear terminal

9. Parallel data input

10. Asynchronous Parallel control of terminal placement
(其实我也不知道对不对。。。）