4级伪随机码发生器的电路，码发生循环的长度15，全0时会发生什么情况

Question

如题所述

Answer 1

你是想有人替你把整个设计报告做好？一般谁有那么闲着啊
我把我的伪随机序列发生器的代码贴出来，完整工程你留下邮箱，我发给你，里面有你想要的，包括码字、波形图、原理图、FPGA工程……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY m_order IS
PORT(clk, reset: IN STD_LOGIC;
choice: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
psout: OUT STD_LOGIC
);
END m_order;
ARCHITECTURE behav OF m_order IS
SIGNAL q : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
REG: PROCESS(clk, reset, choice)
BEGIN
IF reset = '1' THEN
q <= "";
ELSIF clk'EVENT AND clk = '1' THEN
q(5 DOWNTO 1) <= q(4 DOWNTO 0);
END IF;
CASE choice IS
WHEN "00" => q(0) <= '1';
WHEN "01" => q(0) <= NOT(q(5) XOR q(2));
WHEN "10" => q(0) <= NOT(q(5) XOR q(4) XOR q(2) XOR q(1));
WHEN "11" => q(0) <= NOT(q(5) XOR q(4) XOR q(3) XOR q(2));
WHEN OTHERS => NULL;
END CASE;
END PROCESS REG ;
psout <= q(5);
END behav;本回答被提问者采纳