VHDL编程问题,高手进来帮帮忙!!!数字闹钟问题,详细如下,这个程序可行吗?不行的话可否给我可行的给我

我想写一个一个模块,功能是这样的:sp2是由闹钟模块输出的闹钟信号,pass和stop是两个按键,stop按下蜂鸣器停止,pass按下后蜂鸣器停止。但是3分钟后会再响,响5次之后就不会再响了。我自己写了个模块,老是报错,报错信息:can't determine definition of operator ""+"" -- found 0 possible definitions。求高手帮忙解决。程序如下
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lanren is
port(clk,sp2,pass,stop: in std_logic;
sp :out std_logic );
end entity lanren;
ARCHITECTURE art OF lanren IS
signal a: std_logic;
begin
process(clk,sp2,pass,stop)
begin
if (clk'event and clk='1')then
if(sp2='1') then
if(stop='0' and pass='1')then
sp<='0';
elsif(stop='1' and (pass'event and pass='0'))then
sp<='0';
a<=a+1;
sp<='1' after 180 sec;
end if;
if(a>='4') then
a<='0';
sp<='0';
end if;
end if;
sp<=sp2;
end if;
end process;
end ARCHITECTURE art;

你的代码没法综合的
一个process里边只能有一个EVENT, 一般都是用在clock signal
sp<='1' after 180 sec; 这个after只能用在testbench

LIBRARY ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;

entity lanren is
port(clk : in std_logic;
sp2 : in std_logic;
pass : in std_logic;
stop : in std_logic;
sp :out std_logic );
end entity lanren;

ARCHITECTURE art OF lanren IS

type ctrl_type is (s_idle, s_pass, s_rtn);
signal ctrl_state : ctrl_type := s_idle;

signal a: unsigned(2 downto 0) := (others=>'0');
signal pass_cnt : unsigned(9 downto 0) := (others=>'0');

begin

process(clk,sp2,pass,stop)
begin
if rising_edge(clk) then
sp <= '0';
case ctrl_state is
when s_idle =>
if sp2 = '1' then
if stop = '1' then
ctrl_state <= s_rtn;
elsif pass = '1' then
ctrl_state <= s_pass;
end if;
end if;
sp <= sp2;
a <= (others=>'0');
pass_cnt <= (others=>'0');

when s_pass =>
if a = 5 then -- alarm 5 times
ctrl_state <= s_rtn;
else
if pass_cnt(pass_cnt'left) = '1' then -- delay for 3 min, need to adjust the delay cnt according to clk freq
pass_cnt <= (others=>'0');
sp <= '1'; -- alarm once every 3 min, (only last one cycle, if needs longer, add another state )
a <= a + 1;
else
pass_cnt <= pass_cnt + 1;
end if;
end if;

when s_rtn =>
if sp2 = '0' then -- go back when alarm goes off
ctrl_state <= s_idle;
end if;

when others =>
ctrl_state <= s_idle;

end case;
end if;
end process;
end ARCHITECTURE art;
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