library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count1 is
port
(ci:in std_logic; --计数信号
reset: in std_logic; --异步复位
load: in std_logic; --同步置数
clk: in std_logic;
d : in std_logic_vector(3 downto 0); --置数值
q : buffer std_logic_vector(3 downto 0);
co: out std_logic --计数溢出标志
);
end count1;
architecture behave of count1 is
begin
process(clk,reset)
begin
if(reset='0') then
q<="0000";
elsif(clk'event and clk='1') then
if(load='1') then
q<=d;
elsif(ci='1') then
if(q=0) then
q<="1111";
co<='1';
else
q<=q-1;
co<='0';
end if;
end if;
end if;
end process;
end behave;
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