vhdl设计一个具有清零、使能控制的4位十进制计数器

Question

如题所述

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity CNT10 is
port
(
PI_SYSCLK :in std_logic;
PI_EN :in std_logic;
PI_CLR :in std_logic;
PO_CNT :out std_logic_vector(3 downto 0)
);
end entity CNT10;

architecture ARC of CNT10 is
signal S_CNT : std_logic_vector(3 downto 0);
begin
CNT10_PROCESS:process(PI_SYSCLK)
begin
if PI_SYSCLK'event and PI_SYSCLK='1' then
if PI_CLR ='1' then
S_CNT <=(others=>'0');
elsif S_CNT="1001" then
S_CNT <=(others=>'0');
else
S_CNT <=S_CNT + '1';
end if;
end process;
end ARC;追问

你写的是模是10的四位二进制计数器（一位十进制）....