LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD_CTRL IS
PORT ( CLK :IN STD_LOGIC;
AT,BT : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END JTD_CTRL;
ARCHITECTURE JTD OF JTD_CTRL IS
SIGNAL Q :STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS(CLK,AT,BT)
BEGIN
IF CLK'EVENT AND CLK ='1' THEN
IF(AT =X"01")OR (BT = X"01") THEN Q<=Q+1;
ELSE Q<=Q;
END IF;
END IF;
END PROCESS;
S<=Q;
END JTD;