请问怎样用VHDL语言实现,当输入A由0跳变为1时,输出一个时钟宽度的脉冲信...答:ENTITY mono IS PORT (A,clk: IN Bit;P_OUT: OUT Bit);END mono;ARCHITECTURE mono_arch OF mono IS COMPONENT dff PORT(d,ck: IN Bit; q, q_b: OUT Bit);END COMPONENT;SIGNAL sta1, sta2: Bit;BEGIN U1: dff PORTMAP(A, clk, sta1, OPEN);U2: dff PORTMAP(d => sta1, q...