数字钟vhdl程序代码源

Question

如题所述

Answer 1

use ieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clock_shu is
port(
clk : in std_logic;
reset : in std_logic;
duan : out std_logic_vector(5 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end;

architecture a of clock_shu is
component count60
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end component;

component count24
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end component;

component i60bcd
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;

component i24bcd
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end component;
signal carry1,carry2 : std_logic;
signal abin1,abin2 : integer range 0 to 59;
signal abin3 : integer range 0 to 23;
signal clk_1h : std_logic;
signal sh,sl,mh,ml,hh,hl : std_logic_vector(7 downto 0);
signal cnt : integer range 0 to 5 :=0;
begin
process(clk)--分频为1hz
constant counter_len:integer:=19999999;
variable cnt:integer range 0 to counter_len;
begin
if clk'event and clk='1' then
if cnt=counter_len then
cnt:=0;
else
cnt:=cnt+1;
end if;
case cnt is
when 0 to counter_len/2=>clk_1h<='0';
when others =>clk_1h<='1';
end case;
end if;
end process;

process(clk)
variable cnt1 : integer range 0 to 200;
variable cnt2 : integer range 0 to 10;
begin
if clk'event and clk='1' then
if cnt1=200 then
cnt1:=0;
if cnt2=10 then
cnt2:=0;
if(cnt=5)then
cnt<=0;
else
cnt<=cnt+1;
end if;
else
cnt2:=cnt2+1;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end process;

process(clk)
begin
if clk='1' then
case cnt is
when 0 => duan<="000001";data_o<=sl;
when 1 => duan<="000010";data_o<=sh;
when 2 => duan<="000100";data_o<=ml;
when 3 => duan<="001000";data_o<=mh;
when 4 => duan<="010000";data_o<=hl;
when 5 => duan<="100000";data_o<=hh;
when others=>duan<="000000";
end case;
end if;
end process;
u1 : count60 port map(carry=>clk_1h,rst=>reset,times=>abin1,full=>carry1);
u2 : count60 port map(carry=>carry1,rst=>reset,times=>abin2,full=>carry2);
u3 : count24 port map(carry=>carry2,rst=>reset,times=>abin3);
u4 : i60bcd port map(interg=>abin1,ten=>sh,one=>sl);
u5 : i60bcd port map(interg=>abin2,ten=>mh,one=>ml);
u6 : i24bcd port map(interg=>abin3,ten=>hh,one=>hl);
end;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count60 is--分，秒计数器
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end;

architecture a of count60 is
signal time_s : integer range 0 to 59;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
full<='0';
elsif rising_edge(carry) then
if time_s=59 then
time_s<=0;
full<='1';
else
time_s<=time_s+1;
full<='0';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count24 is--时计数器
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end;

architecture a of count24 is
signal time_s : integer range 0 to 23;
begin
process(rst,carry)
begin
if rst='1' then
time_s<=0;
--full<='0';
elsif rising_edge(carry) then
if time_s=23 then
time_s<=0;
--full<='1';
else
time_s<=time_s+1;
--full<='1';
end if;
end if;
end process;
times<=time_s;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity i60bcd is--分，秒显示
port(
interg : in integer range 0 to 59;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;

architecture a of i60bcd is
begin
process(interg)
begin
case interg is
when 0|10|20|30|40|50 => one<="11000000";
when 1|11|21|31|41|51 => one<="11111001";
when 2|12|22|32|42|52 => one<="10100100";
when 3|13|23|33|43|53 => one<="10110000";
when 4|14|24|34|44|54 => one<="10011001";
when 5|15|25|35|45|55 => one<="10010010";
when 6|16|26|36|46|56 => one<="10000011";
when 7|17|27|37|47|57 => one<="11111000";
when 8|18|28|38|48|58 => one<="10000000";
when 9|19|29|39|49|59 => one<="10011000";
when others => one<=null;
end case;

case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23|24|25|26|27|28|29 => ten<="10100100";
when 30|31|32|33|34|35|36|37|38|39 => ten<="10110000";
when 40|41|42|43|44|45|46|47|48|49 => ten<="10011001";
when 50|51|52|53|54|55|56|57|58|59 => ten<="10010010";
when others => ten<=null;
end case;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity i24bcd is--时显示
port(
interg : in integer range 0 to 23;
ten : out std_logic_vector(7 downto 0);
one : out std_logic_vector(7 downto 0)
);
end;

architecture a of i24bcd is
begin
process(interg)
begin
case interg is
when 0|10|20 => one<="11000000";
when 1|11|21 => one<="11111001";
when 2|12|22 => one<="10100100";
when 3|13|23 => one<="10110000";
when 4|14 => one<="10011001";
when 5|15 => one<="10010010";
when 6|16 => one<="10000011";
when 7|17 => one<="11111000";
when 8|18 => one<="10000000";
when 9|19 => one<="10011000";
when others => one<=null;
end case;

case interg is
when 0|1|2|3|4|5|6|7|8|9 => ten<="11000000";
when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";
when 20|21|22|23 => ten<="10100100";
when others => ten<=null;
end case;
end process;
end;

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECONDb is
port(clk,clrm,stop:in std_logic;----时钟/清零信号
secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end MINSECONDb;

architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic;

begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;
begin

IF CLK'EVENT AND CLK='1'THEN
IF COUNT2>=0 AND COUNT2<10 THEN
COUNT2:=COUNT2+1;
ELSE COUNT2:=0;
DOUT2<= NOT DOUT2;
END IF;
END IF;

if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if stop='1' then
cnt0:=cnt0;
cnt1:=cnt1;
end if;

if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
--elsif cnt0="1001" then
--clk1<=not clk1;
else
cnt0:="0000";

if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
secm1<=cnt1;
secm0<=cnt0;

end process;
end SEC;

秒模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
begin
if clr='1' then----当ckr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
else
cnt0:="0000";

if cnt1<"0101" then----高位小于5时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

分模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin

process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

时模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同时为0时
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位记数累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;
动态扫描模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/
daout:out std_logic_vector(3 downto 0);----------------输出
sel:out std_logic_vector(2 downto 0));-----位选信号
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);----计数信号
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="111") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"111"=>daout<= secm0;----秒个位
when"110"=>daout<= secm1;----秒十位
when"101"=>daout<= sec0;----分个位
when"100"=>daout<= sec1;----分十位
when"011"=>daout<=min0; ----时个位
when"010"=>daout<=min1;----时十位
when"001"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;
报时模块

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号
clk:in std_logic;------高频声控制
q500,qlk:out std_logic);----低频声控制
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
q500<='1';----低频输出为1
else
q500<='0';----否则输出为0
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1';-----高频输出为1
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
显示模块

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号
q:out std_logic_vector(6 downto 0));----输出段选信号（电平）
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";--显示0
when"0001" =>q<="0000110";--显示1
when"0010" =>q<="1011011";--显示2
when"0011" =>q<="1001111";--显示3
when"0100" =>q<="1100110";--显示4
when"0101" =>q<="1101101";--显示5
when"0110" =>q<="1111101";--显示6
when"0111" =>q<="0100111";--显示7
when"1000" =>q<="1111111";--显示8
when others =>q<="1101111";--显示9
end case;
end process;
end disp_are;
顶层文件（原理图输入）

********************************************************************
数字钟设计模块与程序（不含秒表）
*********************************************************************
1.分频模块（原理图输入）

2. 秒模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

3.分模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

4.时模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";
cnt0:="0000";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;

5.扫描模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
daout:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>daout<= sec0;
when"001"=>daout<= sec1;
when"010"=>daout<= min0;
when"011"=>daout<= min1;
when"100"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;

6.显示模块程序

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";
when"0001" =>q<="0000110";
when"0010" =>q<="1011011";
when"0011" =>q<="1001111";
when"0100" =>q<="1100110";
when"0101" =>q<="1101101";
when"0110" =>q<="1111101";
when"0111" =>q<="0100111";
when"1000" =>q<="1111111";
when others =>q<="1101111";
end case;
end process;
end disp_are;

7.定时闹钟模块程序

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;

Answer 3

程序启动，校时，校分使能输入
校对用的加减输入
时分秒显示输出

根据CLK进行“秒”的累加，逐次进行进位判断。“时”就根据“分”的进位判断。这是数字电路连线的思路啦。呵呵

还可以参考一下这个，要方便的多本回答被网友采纳