这个verilogHDL程序哪里有问题啊……是个十进制四位计数器……
module count16 (
qout,clk,clear_n,incr_n,cout
);
output[15:0] qout;
output cout;
input clk; //clock
input clear_n;
input incr_n; //1start or 0stop
reg qout;
always @(posedge clk);
begin
if (clear_n==0) qout <= 0;
else if(incr_n==0) qout <= qout;
else if(incr_n==1)
begin
if(qout[3:0]==9)
begin
qout[3:0] <=0;
if(qout[7:4]==9)
begin
qout[7:4] <=0;
if(qout[11:8]==9)
begin
qout[11:8] <=0;
if(qout[15:12]==9) qout[15:12] <=0;
else
qout[15:12]<=qout[15:12]+1;
end
else
qout[11:8]<=qout[11:8]+1;
end
else
qout[7:4]<=qout[7:4]+1;
end
else
qout[3:0]<=qout[3:0]+1
end
end
endmodule
首先在reg qout处就错了，应该为reg 【15：0】 qout；
其次always @(posedge clk);后面没有分号的，应去掉；
再者 qout[3:0]<=qout[3:0]+1后面缺少分号，应加上；
最后还没有cout输出信号；
我在你的基础上稍微改了下，仿了下是正确的，可以见仿真的波形图
程序如下：
module count16 (
qout,clk,clear_n,incr_n,cout
);
output[15:0] qout;
output cout;
input clk; //clock
input clear_n;
input incr_n; //1start or 0stop
reg [15:0] qout;
reg cout;
always @(posedge clk)
begin
if (clear_n==0)
begin
qout <= 16'b0;
cout <= 1'b0;
end
else begin
if(incr_n==0) qout <= qout;
else
begin
if(qout[3:0]==4'h9)
begin
qout[3:0] <=4'b0;
if(qout[7:4]==4'h9)
begin
qout[7:4] <=4'b0;
if(qout[11:8]==4'h9)
begin
qout[11:8] <=4'h0;
if(qout[15:12]==4'h9)
begin
qout[15:12] <=4'b0;
cout <= 1'b1;
end
else
qout[15:12]<=qout[15:12]+1;
end
else
qout[11:8]<=qout[11:8]+1;
end
else
qout[7:4]<=qout[7:4]+1;
end
else
qout[3:0]<=qout[3:0]+1;
end
end
end
endmodule
