Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
Entity vote is
port(D:in STD_LOGIC_VECTOR(4 downto 0);
S:in bit;
ledout:out STD_LOGIC);
End vote;
Architecture votes of vote is
--Signal x:std_logic_vector(4 downto 0);
--signal y:std_logic;
signal count:std_logic_vector(2 downto 0);
Begin
Process(D,s,count)
Variable middle1,middle2,middle3,middle4,middle5:STD_LOGIC;
Begin
--x<="00000";
if S='0' then
middle1:='0';
middle2:='0';
middle3:='0';
middle4:='0';
middle5:='0';
count<="000";
else
middle1:=D(0);
middle2:=D(1);
middle3:=D(2);
middle4:=D(3);
middle5:=D(4);
end if;
if (middle1'event and middle1='1')then
count<=count+1;
end if;
if (middle2'event and middle2='1') then
count<=count+1;
end if;
if (middle3'event and middle3='1') then
count<=count+1;
end if;
if (middle4'event and middle4='1') then
count<=count+1;
end if;
if (middle5'event and middle5='1') then
count<=count+1;
end if;
if(count>="011" and count<="101") then
ledout<='1';
end if;
end process ;
End votes;
在编译的时候总有错误,就是if (middle1'event and middle1='1')then 这一句。