EDA 实验:基于VHDL设计一个异步清零的占空比为7/9的分频器，求代码。

Question

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Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity div9_7 is
port(
clk:IN std_logic;
rst:IN std_logic;

div9:out std_logic
);
end;

architecture behave of div9_7 is
signal cnt: integer range 0 to 8;
signal temo_div9: std_logic;
begin
process(clk,rst)
if rst='0' then
if clk'event and clk='1' then
cnt <= cnt +1;
if cnt = 6 then
temp_div9 <= ~temp_div9;
elsif cnt = 8 then
cnt <= 0;
temp_div9 <= ~temp_div9;
end if;
end if;
end if;
end process;
div9 <= temp_div9;end behave;