请哪位高手写下：设计含有异步清零和计数使能的二位十进制加减可控计数器的VHDL语言程序，谢谢了。

Question

如题所述

Answer 1

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT10 IS

PORT(CLK:IN STD_LOGIC;

RST:IN STD_LOGIC;

ENA:IN STD_LOGIC;

OUTY:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT:OUT STD_LOGIC);

END CNT10;

ARCHITECTURE behav OF CNT10 IS

SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

P_REG:PROCESS(CLK,RST,ENA)

BENGIN

IF RST='1'THEN CQI<="0000";

ELSIF CLKEVEN AND CLK='1' THEN

IF ENA=’1‘ THEN

IF CQI<"1001" THEN

CQI<=CQI+1;

ELSE CQI<=CQI;

END IF;

END IF;

END IF;

OUTY<=CQI;

END PROCESS P_REG;

COUT<=CQI(0) AND CQI(3);

END behav;