用vhdl语言编程两位十进制加法计数器，有使能端，且低位作为高位的进位，怎么写程序？

Question

如题所述

Answer 1

由于不知道你的输出是什么，就设置了一个q用来记满两个十进制输出方波，呵呵。

library ieee;
use ieee.std_logic_1164.all;

entity counter10 is
port(
clk : in std_logic;
clr : in std_logic;
en : in std_logic;
q : out std_logic);
end entity counter10;

architecture art of counter10 is
signal q_reg : std_logic;
signal counter1 : std_logic_vector(3 downto 0);
signal counter2 : std_logic_vector(3 downto 0);
signal flag : std_logic := '0';
begin
process(clk,en,clr)
begin
if(clr = '0') then
q <= '0';
flag <= '0';
counter1 <= X"0";
counter2 <= X"0";
elsif(clk'event and clk = '1') then
if ((en = '1') and (flag = '0')) then
if(counter1 = X"9") then
counter1 = X"0";
flag <= '1';
else
counter1 <= counter1 + '1';
end if;
end if;
end if;
end process;

process(clk,flag)
begin
if(clk'event and clk = '1') then
if(flag = '1') then
if(counter2 = X"9") then
q_reg <= not q_reg;
counter2 <= '0';
flag <= '0';
else
counter2 <= counter2 + '1';
end if;
end if;
end if;
end process;

q <= q_reg;

end art;